1. Field of the Invention
The present invention relates to a data decoding device, specifically a data decoding device and that realize -high-speed decoding processing.
2. Description of the Related Art
As an image forming system for color printing, a configuration in which a host PC sends image data in which one pixel is represented by an RGB multi-value form is known. In order to reduce the amount of data transferred from the host PC to the image forming system, generally, encoded data obtained by compressing image data within the host PC is transferred to the image forming system, where the encoded data is decoded.
Recently, a higher picture-quality of an image has been required. In order to attain a higher picture-quality of an image, in some images, one pixel has a gradation of more than one byte per pixel. Data of these images is subjected to image compression in order to be transferred from the host PC to the image forming system. As one example of the image compression, there is a well known method in which the host PC separates image data of each pixel into higher-end image data and lower-end image data and compresses each of the higher-end image data and lower-end image data. This method may allow for a higher compression rate, compared with a case where image data is not separated into higher-end image data and lower-end image data. Therefore, the speed to transfer the data from the host PC to the image forming system becomes faster.
In the image forming system, decoding processing is performed to decode encoded data sent from the host PC; decoded multi-valued image data is subjected to color processing such as color space conversion; and the color-processed multi-valued data is subjected to pseudo gradation processing to be converted into binary data that can be outputted by a print head. In the case where image data processing such as decoding processing, color processing and pseudo gradation processing is realized within a system LSI that is central to the control of the whole system, sharing an external main memory connected to the system LSI can reduce cost.
That is because hardware resource such as circuit size and the number of pins of LSI can be reduced, for example, compared with a case where system LSI embedded memories, each being dedicated to decoding processing, color processing or pseudo gradation processing, are used and a case where a plurality of external memories connected to a system LSI are used.
However, in the case where an external main memory connected to a system LSI is shared, the bandwidth of the main memory may be a bottleneck, thereby degrading the processing performance of the image forming controller. Even if the operating frequency of the system LSI is improved by advancing the semiconductor process, it is important in performance to reduce the number of accesses to the main memory when increase of the bandwidth of the main memory does not catch up with the improvement.
In a method to refer to upper one raster in decoding processing, when one pixel is subjected to decoding processing, one read access to a reference pixel occurs. Accordingly, in processing for RGB three colors, three read accesses to a reference pixel occur in total. In image data having gradation data of more than 8 bits per pixel, more memory bandwidth is consumed for read access to a reference pixel, compared to image data having 8 bits per pixel.
A higher memory bandwidth required in decoding processing may degrade performance of decoding processing itself, as well as performance of other image processing carried out in the system LSI.
In order to reduce read accesses to reference pixel data in an external memory connected to a system LSI, Japanese Patent Publication No. 3083493, for example, discloses a configuration in which a buffer to storing reference rasters is provided within the system LSI.
Recently, a higher picture-quality of a print image, a speed-up of printing and a lower cost have been required for the image forming system. To achieve the speed-up, a high compression rate must be realized to reduce the amount of data transferred from the host PC to the image forming system. In data processing within the image forming system, accesses to the external memory connected to the system LSI need to be reduced.
In the art described in Japanese Patent Publication No. 3083493, an on-chip buffer provided within the system LSI can reduce read accesses to reference pixel data. However, this has a great influence on chip cost in a large-format printer that has been recently brought to the market. That is, in the case where an upper reference line is stored in the on-chip buffer in decoding processing, assuming that each of RGB is 16 bits, a memory capacity of the number of pixels on one line multiplied by 48 bits is required. For example, in the case where the resolution is 1200 dpi and the maximum printing width is 60 inches, an on-chip memory capacity of no less than 3.3 M bits is required.
In addition, if compressed image data is decoded with the use of reference data, in the above method that includes separating the data into higher-end bytes and lower-end bytes and compressing the separated data, reference data for decoding also must be separated into higher-end bytes and lower-end bytes. In such a case, when data is read from a RAM in such a way that the data is separated into the higher-end and the lower-end, reading at high speed is impossible. Meanwhile, when data can be read at high speed, the data cannot be separated into the higher-end and the lower-end, thus requiring a large amount of memory capacity.